library IEEE;
use IEEE.std_logic_1164.all;
use work.global_definition.all;

entity memory is
    port (
        clk    : in std_ulogic;
        enable : in std_ulogic;
        opcode : in std_ulogic_vector(1 downto 0);

        addr_ins    : in  std_ulogic_vector(ram_address_width-1 downto 0);
        data_ins    : out std_ulogic_vector(ram_data_width-1 downto 0);

        addr_dat    : in    std_ulogic_vector(ram_data_width-1 downto 0);
		data_dat_in	: in    std_ulogic_vector(ram_data_width-1 downto 0);
		data_dat_out: out   std_ulogic_vector(ram_data_width-1 downto 0);
		
        --data_dat    : inout std_ulogic_vector(ram_data_width-1 downto 0);

        MIO    : out   std_ulogic;
        REQ    : out   std_ulogic;
        WE     : out   std_ulogic;
        RAM_OE : out   std_ulogic;
        RAM_WE : out   std_ulogic;
        ADDR   : out   std_ulogic_vector(ram_address_width-1 downto 0);
        DAT    : inout std_ulogic_vector(ram_data_width-1 downto 0);
		EX_ADDR: out   std_ulogic_vector(12 downto 0);
        EX_DAT : inout std_ulogic_vector(ram_data_width-1 downto 0);

		-- for cache
		cache_miss : out std_ulogic
        ) ;
end entity;  -- memory
